Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers

A digital compensation method is described that allows fractional-N frequency synthesizers to be directly modulated at high data rates while simultaneously achieving good noise performance. The technique allows digital phase/frequency modulation to be achieved at high data rates (> 1 Mbit/s) without mixers or D/A converters in the modulation path. The resulting transmitter design is primarily digital in nature and reduced to its fundamental components — a frequency synthesizer that accurately sets the output frequency, and a digital transmit filter that provides good spectral efficiency. The synthesizer is implemented as a phase locked loop (PLL). To achieve good noise performance with a simple design, the PLL bandwidth is set to a low value relative to the data bandwidth. A digital compensation filter is then used to undo the attenuation of the PLL transfer function seen by the data. This filter adds little complexity to the transmitter architecture since it can be combined with the digital transmit filter; the overall filter is efficiently implemented by using a ROM to perform the required convolution with input data. Measured results from a prototype indicate that good performance, low power operation, and high levels of integration are achieved with the approach. Specifically, a 1.8 GHz transmitter was built that supports data rates in excess of 2.5 Mbit/s using Gaussian Frequency Shift Keying (GFSK), the same modulation method used in the digital enhanced cordless telecommunications (DECT) standard. The phase noise of the unmodulated synthesizer was measured at -132 dBc/Hz at 5 MHz offset from the carrier frequency. (Simulations show that the modulated synthesizer achieves -132 dBc/Hz at 5 MHz offset at 1.25 Mbit/s data rate.) The key circuits in the prototype were implemented on a custom, 0.6 um CMOS IC that consumes 27 mW. Included on the IC are an on-chip filter that requires no tuning or external components, a digital MASH Sigma-Delta converter that achieves low power operation through pipelining, and an asynchronous, 64 modulus divider (prescaler) that supports any divide value between 32 and 63.5 in half cycle increments of its input. An external divide-by-2 prescaler allows the divider to operate at half